1. Field of the Invention
The invention relates generally to timing circuits. In particular, the invention relates to the generation of multiple timing signals that have a resolution of twice the frequency of a clock oscillator driving the circuit.
2. Background Art In computer systems and other relatively complex electronic circuits the need often exists for the generation of complex timing signals. A clock circuit, such as a quartz crystal oscillator. produces a binary clock signal with a period of T.sub.c. Although the clock signal itself is sufficient for timing control in relatively simple circuits in more complex circuits the clock signal is converted into several timing signals that have different forms but have a fixed phase relation to each other.
An example of such a clock generator well known in the prior art, for generating a two-phase clock is illustrated in FIG. 1. A ring is constructed of first through fourth master-slave flip-flops 10, 12, 14, 16. The output of the first flip-flop 10 is connected to the input of the second flip-flop 12 and also provides a timing signal A. Similarly the second flip-flop 12 inputs to the third flip-flop 14 and provides the timing signal B. and the third flip-flop 14 controls the fourth flip-flop 16 and provides the timing signal C. The fourth flip-flop 16 not only provides a timing signal D but also closes the loop by inputting to the first flip-flop 10. The waveforms for the clock signal CLK and the four timing signals A, B. C and D are shown in FIG. 2. The timing signals A, B, C and D provide the necessary timing information but in the interest of reducing the number of timing signals that need to be distributed to the system being controlled, these timing signals are combined into two two-phase clock signals PH0 and PH1. The first two-phase clock signal PH0 is produced by an R/S flip-flop 18 receiving the timing signal A on its set input S and the timing signal C on its reset input R. Similarly. the second two-phase clock signal PH1 is produced by another flip-flop 20 receiving the timing signals B and D on corresponding inputs. One of the advantages of the prior art clock generator of FIG. 1 is that the clock signal CLK does not necessarily have a square waveform that is, a 50duty cycle.
The circuit of FIG. 1 operates as a four-stage shift register containing three 0's and one 1 and is clocked by the clock signal CLK. The initialization of the loop or shift register will not be discussed here. The result is that the "1" or high signal is shifted across one of the master-slave flip-flops 10-16 once per clock period T.sub.c.
One principal disadvantage of the clock generator of FIG. 1 is its speed. The resolution of both the timing signals A, B, C and D and the two-phase clock signals PH0 and PH1 is the period T.sub.c of the clock. For instance if a 10 ns resolution is required then a 1OO MHz crystal oscillator is required. Although high speed crystal oscillators are available they are expensive and have stability and tolerance problems.